1. Technical Field
The present invention relates to a semiconductor memory apparatus, and more particularly, to technology for reliably sensing data stored in a memory cell.
2. Related Art
A phase change random access memory (PCRAM) may perform random accesses while having the characteristic of a non-volatile memory, and may be highly integrated at a low cost. The PCRAM stores information using a phase change material, and may be a non-volatile memory device using a phase change of a phase change material depending on a temperature condition, that is, a resistance change depending on a phase change.
The phase change material may include a material that is in an amorphous state or crystal state depending on temperature. Representative examples of the phase change material may include a chalcogenide alloy such as Ge2Sb2Te5 (GST) formed of germanium (Ge), antimony (Sb), and tellurium (Te). Therefore, the phase change material may be generally referred to as GST.
The PCRAM causes a reversible phase change between the crystal state and the amorphous state of the GST using Joule heating generated by applying a current or voltage to the GST under a specific condition. The crystal state is referred to as a set state where the GST has low resistance like a metal. The amorphous state is referred to as a reset state where the GST has a higher resistance value than in the set state. The GST stores information through the change in resistance value between the crystal state and the amorphous state, and discriminates the stored information by sensing a voltage change depending on a current flowing in the GST or a voltage change based on a current change.
FIG. 1 is a configuration diagram of a conventional phase change memory apparatus.
Referring to FIG. 1, the phase change memory apparatus includes a sensing current supply unit 11, a comparison unit 13, and a memory cell 12. The sensing current supply unit 11 and the comparison unit 13 may together be referred to as a data sensing unit.
The memory cell 12 includes a phase change element R_GST formed of a phase change material and a cell diode D1.
An NMOS transistor MN0 is inserted between the sensing current supply unit 11 and the memory cell 12. The NMOS transistor MN0 serves to clamp a current and voltage supplied to the memory cell 12 according to the voltage level of a selection signal V_CLP. It is assumed that the selection signal V_CLP maintains a specific voltage level.
When the sensing current supply unit 11 supplies a sensing current I_SENSE to the memory cell 12, the level of an output voltage V_SAI depends on the resistance of the phase change element R_GST. As the resistance of the phase change element R_GST increases, the voltage V_SAI rises, and as the resistance of the phase change element R_GST decreases, the voltage V_SAI drops.
The comparison unit 13 is configured to sense the output voltage V_SAI based on a reference voltage VREF, output voltage VOUT. The voltage VOUT depends on whether the voltage V_SAI is higher or lower than the reference voltage VREF.
FIG. 2 is a graph showing a resistance change of a resistive memory cell included in the phase change memory apparatus of FIG. 1, depending on a PVT (Process Voltage Temperature) variation.
FIG. 2 includes a first case 21 in which no PVT variation occurs, a second case 22 showing the change of the output voltage V_STI depending on a variation of the sensing current I_SENSE and variations of the threshold voltages Vth of the cell diode D1 and the NMOS transistor MN0, and a third case 23 showing the change of the resistance value of the memory cell depending on a temperature variation. The first case 21 corresponds to a normal case.
The first case 21 is clearly divided into a case R_RESET in which the phase change element R_GST has a large resistance value and a case R_SET in which the phase change element R_GST has a small resistance value. The case R_RESET indicates a resistance distribution of the reset state, and the case R_SET indicates a resistance distribution of the set state. In the first case 21, although the level of the reference voltage VREF is fixed, there is no problem in sensing the output voltage V_SAI.
In the second case 22, the level of the output voltage V_SAI is increased by variations in the threshold voltages Vth of the cell diode D1 and the NMOS transistor NM0. At this time, a data value that should be sensed as the set state may be sensed as the reset state. That is, although the voltage level of the output voltage V_SAI is higher than in the normal case, a margin for discriminating the set state and the reset state is reduced because the voltage level of the reference voltage VREF is fixed. On the other hand, even when the voltage level of the output voltage V_SAI is lower than in the normal case, the margin for discriminating the set state and the reset state is reduced because the voltage level of the reference voltage VREF is fixed.
The third case 23 shows a case in which the resistance value of the phase change element R_GST gradually decreases as the temperature increases. In particular, the resistance distribution of the reset state is moved toward the resistance distribution of the set state such that a margin in resistance value between the set state and the reset state decreases. At this time, since the voltage level of the reference voltage VREF is fixed, a data value which should be sensed as the reset state may be sensed as the set state.